C868_02 Datasheet, PDF (80/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
The switching rules are only taken into account while the timer is running. As a result,
write actions to the timer registers while the timer is stopped do not lead to compare
actions.
4.7.1.4 Duty Cycle of 0% and 100%
These counting and switching rules ensure a PWM functionality in the full range between
0% and 100% duty cycle (duty cycle = active time / total PWM period). In order to obtain
a duty cycle of 0% (compare state never active), a compare value of T12P+1 has to be
programmed (for both compare modes). A compare value of 0 will lead to a duty cycle
of 100% (compare state always active).
4.7.1.5 Compare Mode of T12
The following figure shows the setting and resetting of the compare state bit CC6xST. In
order to simplify the description, only one out of the three parallel channels is described.
The letter ’x’ in the simplified bit names and signal names indicates that there are more
than one channel. The CC6xST bit is the compare state bit in register CMPSTAT, the bit
CC6xPS represents passive state select bit.
The timer T12 generates pulses indicating events like compare-matches, period-
matches and zero-matches, which are used to set (signal T12_xST_se) and to reset
(signal T12_xST_re) the corresponding compare state bit (CC6xST) according to the
counting direction.
The timer T12 modulation output lines T12xO (two for each channel) can be selected to
be in the active state while the corresponding compare state is ’0’ (with CC6xPS=’0’) or
while the corresponding compare state is ’1’ (with CC6xPS=’1’). The bit COUT6xPS has
the same effect for the second output of the channel. The example is shown without
dead-time.
User’s Manual
4-36
V 0.4, 2002-01