C868_02 Datasheet, PDF (184/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Fail Save Mechanism
6.1.4 Input Clock Selection
The time period for an overflow of the Watchdog Timer is programmable in two ways :
– the input frequency to the Watchdog Timer can be selected via bit WDTIN in
register WDTCON to be either f_SYS/2 or f_SYS/128.
– the reload value WDTREL for the high byte of WDT can be programmed in register
WDTCON.
The period P_WDT between servicing the Watchdog Timer and the next overflow can
therefore be determined by the following formula:
P_WDT =
2^{(1 +WDTIN*6)} * (2¹⁶ - WDTREL * 2⁸)
f_SYS
[6.1]
Table 6-1 lists the possible ranges for the watchdog time which can be achieved using
a certain module clock. Some numbers are rounded to 3 significant digits.
Table 6-1 Watchdog Time Ranges
Reload value
in WDTREL
FF_H
7F_H
00_H
Prescaler for f_SYS
2 (WDTIN = ‘0’)
128 (WDTIN = ‘1’)
40 MHz 20 MHz 16 MHz 40 MHz 20 MHz 16 MHz
12.8 µs 25.6 µs 32.0 µs 819.2 µs 1.64 ms 2.05 ms
1.65 ms 3.3 ms 4.13 ms 105.7 ms 211.3 ms 264 ms
3.28 ms 6.55 ms 8.19 ms 209.7 ms 419.4 ms 524 ms
Note :For safety reasons, the user is advised to rewrite WDTCON each time before the
Watchdog Timer is serviced.
User’s Manual
6-6
V 0.4, 2002-01