C868_02 Datasheet, PDF (154/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
4.9.3 Details about Modes 2 and 3
Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission,
the 9th data bit (TB8) can be assigned the value of 0 or 1. On reception, the 9th data bit
goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the
system frequency in mode 2 (When bit SMOD in SFR PCON.7 is set, the baud rate is
f_SYS/32). In mode 3 the baud rate clock is generated by timer 1, which is incremented by
a rate of f_SYS/12 or by the internal baud rate generator.
Figure 4-39 shows a functional diagram of the serial port in modes 2 and 3. The receive
portion is exactly the same as in mode 1. The transmit portion differs from mode 1 only
in the 9th bit of the transmit shift register. The associated timings for transmit/receive are
illustrated in Figure 4-40.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
"Write-to-SBUF" signal also loads TB8 into the 9th bit position of the transmit shift
register and flags the TX control unit that a transmission is requested. Transmission
starts at the next rollover in the divide-by-16 counter. (Thus, the bit times are
synchronized to the divide-by-16 counter, not to the "Write-to-SBUF" signal.)
The transmission begins with activation of SEND, which puts the start bit at TxD. One bit
time later, DATA is activated, which enables the output bit of the transmit shift register to
TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop
bit) into the 9th bit position of the shift register. Thereafter, only zeroes are clocked in.
Thus, as data bits shift out to the right, zeroes are clocked in from the left. When TB8 is
at the output position of the shift register, then the stop bit is just to the left of TB8, and
all positions to the left of that contain zeroes. This condition flags the TX control unit to
do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-
16 rollover after "Write-to-SBUF".
Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is
sampled at a rate of 16 times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and 1FF_H is written
to the input shift register.
At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value
of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If
the value accepted during the first bit time is not 0, the receive circuits are reset and the
unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is
shifted into the input shift register, and reception of the rest of the frame will proceed.
As data bit come from the right, 1s shift out to the left. When the start bit arrives at the
leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags
the RX control block to do one last shift, load SBUF and RB8, and to set RI. The signal
to load SBUF and RB8, and to set RI, will be generated if, and only if, the following
conditions are met at the time the final shift pulse is generated:
User’s Manual
4-110
V 0.4, 2002-01