HYB18T512400AC5 Datasheet, PDF (90/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
Table 42 Input Setup (t_IS) and Hold (t_IH) Time Derating Table
Command / Address
Slew rate (V/ns)
CK, CK Differential Slew Rate
Units Notes
1)
2.0 V/ns
1.5 V/ns
1.0 V/ns
∆ t_IS
∆ t_IH
∆ t_IS
∆ t_IH
∆ t_IS
∆ t_IH
4.0
187
94
217
124
247
154
ps
3.5
179
89
209
119
239
149
ps
3.0
167
83
197
113
227
143
ps
2.5
150
75
180
105
210
135
ps
2.0
125
45
155
75
185
105
ps
1.5
83
21
113
51
143
81
ps
1.0
0
0
30
30
60
60
ps
0.9
–11
–14
19
16
49
46
ps
0.8
–25
–31
5
–1
35
29
ps
0.7
–43
–54
–13
–24
17
6
ps
0.6
–67
–83
–37
–53
–7
–23
ps
0.5
–110 –125
–80
–95
–50
–65
ps
0.4
–175 –188
–145
–158
–115
–128
ps
0.3
–285 –292
–255
–262
–225
–232
ps
0.25
–350 –375
–320
–345
–290
–315
ps
0.2
–525 –500
–495
–470
–465
–440
ps
0.15
–800 –708
–770
–678
–740
–648
ps
0.1
–1450 –1125 –1420 –1095 –1390 –1065 ps
1) For all input signals the total t_IS (input setup time) and t_IH (input hold time) required is calculated by adding the individual
value to the derating value listed in this table.
Data Sheet
90
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P