HYB18T512400AC5 Datasheet, PDF (38/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
01
2 34
5
CK, CK
CMD
DQS,
DQS
DQ
Activate
Bank A
Read
Bank A
AL = 2
CL = 3
tRCD
RL = AL + CL = 5
6
7
8 9 10 11 12
Write
Bank A
WL = RL -1 = 4
Dout0
Dout1
Dout2
Dout3
Dout4
Dout5
Dout6
Dout7
Din0
Din1
Din2
Din3
PostCAS3
Figure 20 Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read
delay < t_RCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8
01
2
CK, CK
CMD
DQS,
DQS
Activate
Bank A
DQ
tRCD
34
5
AL = 0
Read
Bank A
CL = 3
RL = AL + CL = 3
6
7
8 9 10 11
Write
Bank A
WL = RL -1 = 2
Dout0
Dout1
Dout2
Dout3
Din0
Din1
Din2
Din3
PostCAS2
Figure 21 Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read
delay = t_RCDmin: AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4
01
2 34
5
6
CK, CK
CMD
DQS,
DQS
Activate
Bank A
tRCD > tRCDmin.
DQ
Read
Bank A
RL = 4
7
8 9 10
Write
Bank A
WL = 3
Dout0
Dout1
Dout2
Dout3
11 12 13
Din0
Din1
Din2
Din3
PostCAS5
Figure 22 Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read
delay > t_RCDmin: AL = 1, CL = 3, RL = 4, WL = 3, BL = 4
2.6.2 Burst Mode Operation
Burst mode operation is used to provide a constant flow
of data to memory locations (write cycle), or from
memory locations (read cycle). The parameters that
define how the burst mode will operate are burst
sequence and burst length. The DDR2 SDRAM
supports 4 bit and 8 bit burst modes only. For 8 bit burst
mode, full interleave address ordering is supported,
however, sequential address ordering is nibble based
for ease of implementation. The burst length is
programmable and defined by the addresses A[2:0] of
the MRS. The burst type, either sequential or
interleaved, is programmable and defined by the
Data Sheet
38
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P