HYB18T512400AC5 Datasheet, PDF (39/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
address bit 3 (A3) of the MRS. Seamless burst read or
write operations are supported. Interruption of a burst
read or write operation is prohibited, when burst length
= 4 is programmed. For burst interruption of a read or
write burst when burst length = 8 is used, see the
Chapter 2.6.6. A Burst Stop command is not supported
on DDR2 SDRAM devices.
Table 12 Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
4
000
001
010
011
8
000
001
010
011
100
101
110
111
Sequential Addressing
(decimal)
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
Interleave Addressing
(decimal)
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Note:
1. Page length is a function of I/O organization: 128Mb X 4 organization (CA[9:0], CA11); Page Length = 1 kByte;
64Mb X 8 organization (CA[9:0]); Page Length = 1 kByte; 32Mb X 16 organization (CA[9:0]); Page Length = 2
kByte
2. Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR or DDR
components
2.6.3 Read Command
The Read command is initiated by having CS and CAS
low while holding RAS and WE high at the rising edge
of the clock. The address inputs determine the starting
column address for the burst. The delay from the start
of the command until the data from the first cell appears
on the outputs is equal to the value of the read latency
(RL). The data strobe output (DQS) is driven low one
clock cycle before valid data (DQ) is driven onto the
data bus. The first bit of the burst is synchronized with
the rising edge of the data strobe (DQS). Each
subsequent data-out appears on the DQ pin in phase
with the DQS signal in a source synchronous manner.
The RL is equal to an additive latency (AL) plus CAS
latency (CL). The CL is defined by the Mode Register
Set (MRS). The AL is defined by the Extended Mode
Register Set (EMRS(1)).
Data Sheet
39
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P