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| HYB18T512400AC5 Datasheet, PDF (13/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM | |||
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HYB18T512[400/800/160]A[C/F]â[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Overview
1
2
3
4
5
6
7
8
9
VDD
NC
VSS
NC
VSSQ
DM
VDDQ
DQ1
VDDQ
NC
VSSQ
DQ3
V DDL
V REF
VSS
CKE
WE
A
VSSQ
DQS
VDDQ
B
DQS
VSSQ
NC
C
V DDQ
DQ0
VDDQ
D
DQ2
VSSQ
NC
E
V SSDL
CK
V DD
F
RAS
CK
ODT
NC/BA2 BA0
BA1
G
CAS
CS
A10/AP A1
H
A2
A0
V DD
V SS
A3
A5
J
A6
A4
A7
A9
K
A11
A8
VSS
Figure 1
VDD
A12
NC
L
NC NC/A13
Pin Configuration P-TFBGA-60 (Ã4) Top View, see the balls throught the package
MPPT0010
Notes
1. VDDL and VSSDL are power and ground for the
DLL.They are isolated on the device from VDD,
VDDQ, VSS and VSSQ.
2. Ball position G1 is Not Connected and will be used
for BA2 on 1-Gbit memory densities and higher
3. Ball position L8 is A13 for 512-Mbit and higher and
is Not Connected on 256-Mbit
Data Sheet
13
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
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