HYB18T512400AC5 Datasheet, PDF (36/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
respectively. The minimum time interval between
successive Bank Activate commands to the same bank
is determined (t_RC). The minimum time interval between
Bank Active commands, to any other bank, is the Bank
A to Bank B delay time (t_RRD).
In order to ensure that components with 8 internal
memory banks do not exceed the instantaneous
current supplying capability, certain restrictions on
operation of the 8 banks must be observed. There are
two rules.
One for restricting the number of sequential Active
commands that can be issued and another for allowing
more time for RAS precharge for a Precharge-All
command. The rules are as follows:
1. Sequential Bank Activation Restriction (JEDEC
ballot item 1293.15): No more than 4 banks may be
activated in a rolling t_FAW window. Converting to
clocks is done by deviding t_FAW(ns) by t_CK(ns) and
rounding up to next integer value. As an example of
the rolling window, if (t_FAW/t_CK) rounds up to 10
clocks, and an activate command is issued in clock
N, no more than three further activate commands
may be issued in clocks N + 1 through N + 9.
2. Precharge All Allowance: t_RP for a Precharge-All
command will equal to t_RP + 1 t_CK, where t_RP is the
value for a single bank precharge.
T
T
T
T
T
T
0
1
2
3
4
n
Tn+1
Tn+2
Tn+3
CK, CK
Internal RAS-CAS delay tRCDmin.
Address
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank A to Bank B delay tRRD.
additive latency AL=2
Bank B
Col. Addr.
Read A Begins
Bank A
NOP
Bank B
Bank A
Addr.
Addr.
Row Addr.
Command
Bank A
Activate
Posted CAS
Read A
Bank B
Activate
Posted CAS
Read B
tRAS Row Active Time (Bank A)
tCCD
Bank A
NOP
Bank B
Bank A
Precharge
Precharge
Activate
tRP Row Precharge Time (Bank A)
tRC Row Cycle Time (Bank A)
ACT
Figure 17 Bank Activate Command Cycle: t_RCD = 3, AL = 2, t_RP = 3, t_RRD = 2
2.6
Read and Write Commands and Access Modes
After a bank has been activated, a read or write cycle
can be executed. This is accomplished by setting RAS
high, CS and CAS low at the clock’s rising edge. WE
must also be defined at this time to determine whether
the access cycle is a read operation (WE high) or a
write operation (WE low). The DDR2 SDRAM provides
a wide variety of fast access modes. A single Read or
Write Command will initiate a serial read or write
operation on successive clock cycles at data rates of up
to 667 Mb/sec/pin for main memory. The boundary of
the burst cycle is restricted to specific segments of the
page length.
For example, the 32Mbit × 4 I/O × 4 Bank chip has a
page length of 2048 bits (defined by CA[9:0] & CA11).
In case of a 4-bit burst operation (burst length = 4) the
page length of 2048 is divided into 512 uniquely
addressable segments (4-bits × 4 I/O each). The 4-bit
burst operation will occur entirely within one of the 512
segments (defined by CA[8:0] beginning with the
column address supplied to the device during the Read
or Write Command (CA[9:0] & A11). The second, third
and fourth access will also occur within this segment,
however, the burst order is a function of the starting
address, and the burst sequence.
In case of a 8-bit burst operation (burst length = 8) the
page length of 2048 is divided into 256 uniquely
addressable double segments (8-bits × 4 I/O each).
The 8-bit burst operation will occur entirely within one
of the 256 double segments (defined by CA[7:0])
Data Sheet
36
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P