HYB18T512400AC5 Datasheet, PDF (8/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Overview
A 16-bit address bus for ×4 and ×8 organised
components and a 15-bit address bus for ×16
components is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is
provided along with various power-saving power-down
modes.
The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The DDR2 SDRAM is available in P-TFBGA package.
1.3
Ordering Information
Table 2 Ordering information
Part Number
Org. Speed
HYB18T512400AC–5 x4 DDR2–400
HYB18T512800AC–5 x8
HYB18T512160AC–5 x16
HYB18T512400AC–3.7 x4 DDR2–533
HYB18T512800AC–3.7 x8
HYB18T512160AC–3.7 x16
CAS-RCD-RP
Latencies
3–3–3
4–4–4
Clock
(MHz)
200
266
CAS-RCD-RP
Latencies
—
3–3–3
Clock
(MHz)
—
200
Package
P-TFBGA-60-6
P-TFBGA-84-1
P-TFBGA-60-6
P-TFBGA-84-1
HYB18T512400AF–5 x4 DDR2–400 3–3–3
200
HYB18T512800AF–5 x8
HYB18T512160AF–5 x16
HYB18T512400AF–3.7 x4 DDR2–533 4–4–4
266
HYB18T512800AF–3.7 x8
HYB18T512160AF–3.7 x16
Note: For product nomenclature see Chapter 10 of this data sheet
—
3–3–3
—
P-TFBGA-60-6
P-TFBGA-84-1
200 P-TFBGA-60-6
P-TFBGA-84-1
Data Sheet
8
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P