HYB18T512400AC5 Datasheet, PDF (32/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
ODT Truth Tables
The ODT Truth Table shows which of the input pins are
terminated depending on the state of address bit A10
and A11 in the EMRS(1) for all three device
organisations (×4, ×8 and ×16). To activate termination
of any of these pins, the ODT function has to be
enabled in the EMRS(1) by address bits A6 and A2.
Table 11 ODT Truth Table
Input Pin
EMRS(1)
Address Bit A10
×4 components
DQ[3:0]
X
DQS
X
DQS
0
DM
X
×8 components
DQ[7:0]
X
DQS
X
DQS
0
RDQS
X
RDQS
0
DM
X
×16 components
DQ[15:0]
X
LDQS
X
LDQS
0
UDQS
X
UDQS
0
LDM
X
UDM
X
EMRS(1)
Address Bit A11
X
X
X
X
X
X
X
1
1
0
X
X
X
X
X
X
X
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
ODT timing modes
Depending on the operating mode synchronous or
asynchronous ODT timings apply. Synchronous
timings (t_AOND, t_AOFD, t_AON and t_AOF) apply for all modes,
when the on-die DLL is enabled.
These modes are:
• Active Mode
• Standby Mode
• Fast Exit Active Power Down Mode (with MRS bit
A12 is set to “0”)
Asynchronous ODT timings (t_AOFPD, t_AONPD) apply when
the on-die DLL is disabled.
These modes are:
• Slow Exit Active Power Down Mode (with MRS bit
A12 is set to “1”)
• Precharge Power Down Mode
Data Sheet
32
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P