HYB18T512400AC5 Datasheet, PDF (79/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
I_DD Specifications and Conditions
6.1
I_DD Test Conditions
For testing the I_DD parameters, the following timing parameters are used:
Table 38 IDD Measurement Test Condition
Parameter
Symbol -3.7
-5
Units Notes
DDR2–533 4–4–4 DDR2–400 3–3–3
CAS Latency
CL_min
4
3
t_CK
Clock Cycle Time
t_CKmin
3.75
5
ns
Active to Read or Write delay
t_RCDmin
15
15
ns
Active to Active / Auto-Refresh command t_RCmin
60
55
ns
period
Active bank A to Active bank B command t_RRDmin 7.5
7.5
ns
1)
delay
10
10
ns
2)
Active to Precharge Command
t_RASmin
45
40
ns
Precharge Command Period
t_RPmin
15
15
ns
Auto-Refresh to Active / Auto-Refresh
t_RFCmin
105
105
ns
command period
1) ×4 & ×8 (1 kB page size)
2) ×16 (2 kB page size)
6.2
On Die Termination (ODT) Current
The ODT function adds additional current consumption
to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a
“week” or “strong” termination can be selected. The
current consumption for any terminated input pin,
depends on the input pin is in tri-state or driving “0” or
“1”, as long a ODT is enabled during a given period of
time.
.
Table 39 ODT current per terminated input pin:
ODT Current
Enabled ODT current per DQ
I_ODTO
added I_DDQ current for ODT enabled;
ODT is HIGH; Data Bus inputs are FLOATING
Active ODT current per DQ
I_ODTT
added I_DDQ current for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs are
STABLE or SWITCHING.
EMRS(1) State min. typ.
A6 = 0, A2 = 1 5
6
A6 = 1, A2 = 0 2.5 3
A6 = 0, A2 = 1 10 12
A6 = 1, A2 = 0 5
6
max.
7.5
3.75
Unit
mA/DQ
mA/DQ
15 mA/DQ
7.5 mA/DQ
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
79
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P