HYB18T512400AC5 Datasheet, PDF (49/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
DQS,
DQS
DQ
Post CAS
READ A
AL = 1
NOP
NOP
AL + BL/2 clks
CL = 3
RL = 4
> = tR A S
> = tR C
NOP
NOP
P re c h a rg e
NOP
tR P
NOP
Bank A
A ctivate
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7
CL = 3
>=tR TP
first 4-bit prefetch
second 4-bit prefetch
BR-P413(8)
Figure 40 Read Operation Followed by Precharge Example 2:
RL = 4 (AL = 1, CL = 3), BL = 8, t_RTP ≤ 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD Post CAS
READ A
DQS,
DQS
DQ
NOP
NOP
AL + BL/2 clks
NOP
AL = 2
RL = 5
> = tR A S
CL = 3
>=tR C
> = tR T P
P re ch a rg e
NOP
tR P
NOP
Bank A
A c tiv a te
Dout A0 Dout A1 Dout A2 Dout A3
CL = 3
Figure 41 Read Operation Followed by Precharge Example 3:
RL = 5 (AL = 2, CL = 3), BL = 4, t_RTP ≤ 2 clocks
NOP
BR-P523
Data Sheet
49
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P