HYB18T512400AC5 Datasheet, PDF (60/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Power-Down Entry
Active Power-down mode can be entered after an
Activate command. Precharge Power-down mode can
be entered after a Precharge, Precharge-All or internal
precharge command. It is also allowed to enter power-
mode after an Auto-Refresh command or MRS /
EMRS(1) command when t_MRD is satisfied.
Active Power-down mode entry is prohibited as long as
a Read Burst is in progress, meaning CKE should be
kept high until the burst operation is finished. Therefore
Active Power-Down mode entry after a Read or Read
with Auto-Precharge command is allowed after
RL + BL/2 is satisfied.
Active Power-down mode entry is prohibited as long as
a Write Burst and the internal write recovery is in
progress. In case of a write command, active power-
down mode entry is allowed when WL + BL/2 + t_WTR is
satisfied.
In case of a write command with Auto-Precharge,
Power-down mode entry is allowed after the internal
precharge command has been executed, which is WL
+ BL/2 + WR starting from the write with Auto-
Precharge command. In this case the DDR2 SDRAM
enters the Precharge Power-down mode.
T0
T1
T2
CK, CK
Tn
Tn+1
Tn+2
CM D _Activate
CKE
NOP
NOP
tIS
Active
Power-Down
Entry
NOP
NOP
NOP
V alid
C om m and
tIS
tXARD or
tXARDS *)
Active
Power-Down
Exit
Act.PD 0
Figure 54 Active Power-Down Mode Entry and Exit after an Activate Command
Note: Active Power-Down mode exit timing t_XARD (“fast exit”) or t_XARDS (“slow exit”) depends on the programmed
state in the MRS, address bit A12.
T0
T1
T2
T3
T4
T5
T6
T7
T8
Tn
Tn+1 Tn+2
CK, CK
CMD ^READ
NOP
READ w/AP
NOP
NOP
CKE
RL + BL/2
DQS,
DQS
AL = 1 CL = 3
RL = 4
DQ
NOP
NOP
NOP
Dout A0 Dout A1 Dout A2 Dout A3
NOP
NOP
tIS
NOP
NOP
V a lid
C om m and
tIS
tXARD or
tXARDS *)
Active
Power-Down
Entry
Active
Power-Down
Exit
Act.PD 1
Figure 55 Active Power-Down Mode Entry and Exit Example after a Read Command:
RL = 4 (AL = 1, CL =3), BL = 4
Note: Active Power-Down mode exit timing t_XARD (“fast exit”) or t_XARDS (“slow exit”) depends on the programmed
state in the MRS, address bit A12.
Data Sheet
60
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P