HYB18T512400AC5 Datasheet, PDF (63/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.11
Other Commands
2.11.1 No Operation Command
The No Operation Command (NOP) should be used in
cases when the SDRAM is in a idle or a wait state. The
purpose of the No Operation Command is to prevent
the SDRAM from registering any unwanted commands
between operations. A No Operation Command is
registered when CS is low with RAS, CAS, and WE
held high at the rising edge of the clock. A No Operation
Command will not terminate a previous operation that
is still executing, such as a burst read or write cycle.
2.11.2 Deselect Command
The Deselect Command performs the same function as
a No Operation Command. Deselect Command occurs
when CS is brought high, the RAS, CAS, and WE
signals become don’t care.
2.12
Input Clock Frequency Change
During operation the DRAM input clock frequency can
be changed under the following conditions:
• During Self-Refresh operation
• DRAM is in Precharge Power-down mode and ODT
is completely turned off.
The DDR2-SDRAM has to be in Precharged Power-
down mode and idle. ODT must be already turned off
and CKE must be at a logic “low” state. After a minimum
of two clock cycles after t_RP and t_AOFD have been
satisfied the input clock frequency can be changed. A
stable new clock frequency has to be provided, before
CKE can be changed to a “high” logic level again. After
t_XP has been satisfied a DLL RESET command via
EMRS(1) has to be issued. During the following DLL re-
lock period of 200 clock cycles, ODT must remain off.
After the DLL-re-lock period the DRAM is ready to
operate with the new clock frequency.
T0
T1
T2
T3
T4
Tx
Tx+1
Ty
Ty+1
Ty+2 Ty+3
Tz
CK, CK
CMD
CKE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DLL
RESET
NOP
V alid
Com m and
tRP
tAOFD
Minimum 2 clocks
required before
changing the frequency
Frequency Change
occurs here
tXP
Stable new clock
before power-down exit
200 clocks
ODT is off during
DLL RESET
Frequ.Ch.
Figure 61 Input Frequency Change Example during Precharge Power-Down mode
Data Sheet
63
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P