HYB18T512400AC5 Datasheet, PDF (64/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.13
Asynchronous CKE Low Reset Event
In a given system, Asynchronous Reset event can
occur at any time without prior knowledge. In this
situation, memory controller is forced to drop CKE
asynchronously low, immediately interrupting any valid
operation. DRAM requires CKE to be maintained “high”
for all valid operations as defined in this data sheet. If
CKE asynchronously drops “low” during any valid
operation, the DRAM is not guaranteed to preserve the
contents of the memory array. If this event occurs, the
memory controller must satisfy a time delay (t_delay)
before turning off the clocks. Stable clocks must exist at
the input of DRAM before CKE is raised “high” again.
The DRAM must be fully re-initialized as described the
initialization sequence (section 2.2.1, step 4 thru 13).
DRAM is ready for normal operation after the
initialization sequence. See Chapter 7.
stable clocks
CK, CK
tdelay
CKE
CKE drops low due to an
asynchronous reset event
Clocks can be turned off after
this point
Figure 62 Asynchronous Low Reset Event
Data Sheet
64
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P