HYB18T512400AC5 Datasheet, PDF (19/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Overview
Drivers
Receivers
Read Latch
Bank0
Row-Address Latch
& Decoder
Bank Control Logic
Row-Address MUX
Refresh Counter
Address Register
Figure 5 Block Diagram 16 Mbit × 8 I/O × 4 Internal Memory Banks
MPBT0050
Notes
1. 64Mb x 8 Organisation with 14 Row, 2 Bank and 10
Column External Addresses
2. This Functional Block Diagram is intended to
facilitate user understanding of the operation of the
device; it does not represent an actual circuit
implementation.
3. DM is a unidirectional signal (input only), but is
internally loaded to match the load of the
bidirectional DQ and DQS signals.
Data Sheet
19
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P