HYB18T512400AC5 Datasheet, PDF (82/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Electrical Characteristics & AC Timing - Absolute Specification
9) CL = 3
10) CL = 4 & 5
11) For timing definition, slew rate and slew rate derating see Chapter 8.3
12) For timing definition, slew rate and slew rate derating see Chapter 8.3
13) The _tHZ, t_RPST and t_LZ, t_RPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (t_HZ, t_RPST), or begins driving (t_LZ, t_RPRE). _tHZ and t_LZ transitions occur in the same access time windows as
valid data transitions.These parameters are verified by design and characterisation, but not subject to production test.
14) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output slew rate mis-match between DQS / DQS and associated DQ in any given cycle.
15) The maximum limit for this parameter is not a device limit. The device operate with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
16) t_RAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is
equal to 9 x t_REFI.
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The t_RCD timing parameter is valid for both activate command to read or write command with and without Auto-Precharge.
Therefore a separate parameter t_RAP for activate command to read or write command with Auto-Precharge is not necessary
anymore.
19) ×4 & ×8 (1k page size)
20) ×16 (2k page size)
21) For each of the terms, if not already an integer, round to the next highest integer. t_CK refers to the application clock period.
WR refers to the WR parameter stored in the MRS.
22) t_WTR is at least two clocks independent of operation frequency.
23) User can choose two different active power-down modes for additional power saving via MRS address bit A12.
24) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85^oC and 95^oC.
25) 0 ^oC - 85 ^oC
26) 85 ^oC - 95 ^oC
27) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
Table 41 ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition
Min.
Max.
Units Notes
t_AOND
t_AON
t_AONPD
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down
Modes)
2
t_AC(min)
t_AC(min) + 2 ns
2
t_CK
t_AC(max) + 1 ns
ns
1)
2 t_CK + t_AC(max) + 1 ns ns
t_AOFD
t_AOF
t_AOFPD
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down
Modes)
2.5
t_AC(min)
t_AC(min) + 2 ns
2.5
t_CK
t_AC(max) + 0.6 ns
ns
2)
2.5 t_CK + t_AC(max) + 1 ns ns
t_ANPD
ODT to Power Down Mode 3
Entry Latency
—
t_CK
t_AXPD
ODT Power Down Exit Latency 8
—
t_CK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max is when the ODT resistance is fully on. Both are measure from t_AOND.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in
high impedance. Both are measured from t_AOFD.
Data Sheet
82
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P