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| HYB18T512400AC5 Datasheet, PDF (15/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM | |||
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HYB18T512[400/800/160]A[C/F]â[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Overview
1
2
3
4
5
6
7
8
9
VDD
NC
VSS
DQ14
VSSQ
UDM
VDDQ
DQ9
VDDQ
DQ12 VSSQ DQ11
VDD
NC
VSS
DQ6
VSSQ
LDM
VDDQ
DQ1
VDDQ
DQ4
VSSQ
DQ3
V DDL
V REF
VSS
CKE
WE
A
VSSQ UDQS
VDDQ
B
UDQS VSSQ DQ15
C
V DDQ
DQ8
VDDQ
D
UDQ2 VSSQ DQ13
E
VSSQ
LDQS
VDDQ
F
LDQS VSSQ
DQ7
G
V DDQ
DQ0
VDDQ
H
DQ2
VSSQ
DQ5
J
V SSDL
CK
V DD
K
RAS
CK
ODT
NC/BA2 BA0 BA1
L
CAS
CS
A10/AP A1
M
A2
A0
V DD
V SS
A3
A5
N
A6
A4
A7
A9
P
A11
A8
VSS
Figure 3
VDD
A12
NC
R
NC NC/A13
MPPT0110
Pin Configuration P-TFBGA-84 (Ã16) Top View, see the balls throught the package
Notes
1. UDQS/UDQS is data strobe for upper byte,
LDQS/LDQS is data strobe for lower byte
2. UDM is the data mask signal for the upper byte
UDQ[7:0], LDM is the data mask signal for the lower
byte LDQ[7:0]
3. Ball position L1 will be used for BA2 on 1-Gbit
memory densities and higher
Data Sheet
15
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
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