HYB18T512400AC5 Datasheet, PDF (43/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
DQS,
DQS
Figure 29 Basic Write Timing
t DQSH
DQS
DQS
t WPRE
t DQSL
Din
Din
Din
t _DS
t DH
t _WPST
Din
T0
T1
T2
T3
CK, CK
CMD
Post CAS
W R IT E A
NOP
NOP
NOP
DQS,
DQS
DQ
WL = RL-1 = 4
T4
T5
T6
T7
T9
NOP
NOP
<= tDQSS
NOP
NOP
C om pletion of
the Burst W rite
tW R
DIN A0 DIN A1 DIN A2 DIN A3
P recharge
BW543
Figure 30 Example Timing Diagram : Write Operation: RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
CMD Post CAS
NOP
W RITE A
DQS,
DQS
DQ
WL = RL-1 = 2
NOP
NOP
<= tDQSS
NOP
NOP
NOP
Com pletion of
the Burst W rite
DIN A0 DIN A1 DIN A2 DIN A3
tW R
P re ch a rg e
Bank A
A c tiv a te
tR P
BW322
Figure 31 Write Operation Example: RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
Data Sheet
43
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P