HYB18T512400AC5 Datasheet, PDF (47/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
READ A
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
DQ
Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6 Dout B7
RBI
Figure 37 Read Interrupt Timing Example 1: (CL = 3, AL = 0, RL = 3, BL = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
NOP
W RITE A
NOP
W RITE B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
DQ
Din A0 Din A1 Din A2 Din A3 Din B0 Din B1 Din B2 Din B3 Dout B4 Din B5 Din B6 Din B7
WBI
Figure 38 Write Interrupt Timing Example 2: (CL = 3, AL = 0, WL = 2, BL = 8)
Data Sheet
47
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P