HYB18T512400AC5 Datasheet, PDF (27/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
The DLL must be enabled for normal operation. DLL
enable is required during power up initialization, and
upon returning to normal operation after having the DLL
disabled. The DLL is automatically disabled when
entering Self-Refresh operation and is automatically re-
enabled upon exit of Self-Refresh operation. Any time
the DLL is enabled (and subsequently reset), 200 clock
cycles must occur before a Read command can be
issued to allow time for the internal clock to be
synchronized with the external clock. Failing to wait for
synchronization to occur may result in a violation of the
t_AC or t_DQSCK parameters.
Output Disable (Qoff)
Under normal operation, the DRAM outputs are
enabled during Read operation for driving data (Qoff bit
in the EMRS(1) is set to 0). When the Qoff bit is set to
1, the DRAM outputs will be disabled. Disabling the
DRAM outputs allows users to measure IDD currents
during Read operations, without including the output
buffer current.
2.2.4 EMRS(2)
The Extended Mode Registers EMRS(2) and EMRS(3)
are reserved for future use and must be programmed
when setting the mode register during initialization.
The extended mode register(2) controls refresh related
features. The default value of the extended mode reg-
ister(2) is not defined, therefore the extended mode
register(2) must be written after Power-up for proper
operation.
The extended mode register EMRS(2) is written by
asserting low on CS, RAS, CAS, WE, BA0 and high on
BA1,while controlling the states of the address pins.
The DDR2 SDRAM should be in all bank precharge
with CKE already high prior to writing into the extended
mode register(2). The mode register set command
cycle time (t_MRD) must be satisfied to complete the write
operation to the extended mode register(2). Mode
register contents can be changed using the same
command and clock cycle requirements during normal
operation as long as all banks are in precharge state.
EMRS(2) Programming
Extended Mode Register Definition
(BA[1:0] = 01_B)
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1
0
0¹⁾²⁾
1) A13 is only available for ×4 and ×8 configuration.
2) Must be programmed to “0”
reg.addr
2.2.5 EMRS(3)
The Extended Mode Register EMRS(3) is reserved for
future use and all bits except BA0 and BA1 must be
programmed to 0 when setting the mode register during
initialization.
EMRS(3) Programming
Extended Mode Register Definition
(BA[1:0] = 01_B)
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1
1
0¹⁾²⁾
1) A13 is only available for ×4 and ×8 configuration.
2) Must be programmed to “0”
reg. addr
Data Sheet
27
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P