HYB18T512400AC5 Datasheet, PDF (28/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.3
Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and
the flow chart below is an example of the sequence.
Every calibration mode command should be followed
by “OCD calibration mode exit” before any other
command being issued. MRS should be set before
entering OCD impedance adjustment and On Die
Termination (ODT) should be carefully controlled
depending on system environment.
Start
EMRS: OCD calibration mode exit
EMRS: Drive (1)
DQ & DQS High; DQS Low
EMRS: Drive (0)
DQ & DQS Low; DQS High
ALL OK
Test
Need Calibration
EMRS: OCD calibration mode exit
EMRS:
Enter Adjust Mode
ALL OK
Test
Need Calibration
EMRS: OCD calibration mode exit
EMRS:
Enter Adjust Mode
BL = 4 code input to all DQs
Inc, Dec or NOP
BL = 4 code input to all DQs
Inc, Dec or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
Figure 9 OCD Impedance Adjustment Flow Chart
MPFT0020
Note
1. MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled
depending on system environment
Data Sheet
28
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P