HYB18T512400AC5 Datasheet, PDF (88/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
CK ,DQS
CK ,DQS
V _DDQ
V _{IH (ac)} min
V _{IH (dc)} min
V _REF(dc)
V _{IL (dc)} max
V _{IL (ac)} max
Dc to VREF
region
Dc to VREF
region
t _IS ,t _DS
Nominal
slew rate
tIH _{,t DH}
t _IS ,t _DS tIH ,t _DH
Nominal
slew rate
V _SS
Delta TR
Delta TF
Hold Slew Rate ₌ ^{VIH(dc)min - VREF(dc)}
Falling Signal
Delta TF
Hold Slew Rate ₌ ^{VREF(dc) - VIL(dc)max}
Rising Signal
Delta TR
Figure 72 Slew Rate Definition Nominal Diagram for t_IH(t_DH)
Note: DQS, DQS signals must be monotonic between V_IL(dc)max and V_IH(dc)min.
Data Sheet
88
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P