HYB18T512400AC5 Datasheet, PDF (23/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
CK, CK
CKE
ODT "low"
NOP
400 ns tRP ^tMRS tMRS tMRS ^tMRS
Follow OCD
tRP
tRFC tRFC tMRS
flowchart
tMRS
PRE
ALL
EMRS(2)
EMRS(3)
EMRS(1)
MRS
PRE
ALL
1st Auto
refresh
2nd Auto
refresh
MRS
EMRS(1)
OCD
min. 200 cycles to lock the DLL
EMRS(1)
OCD
Any
Command
Extended
Mode
Register(1) Set
with DLL enable
Mode
Register
Set with
DLL reset
Mode
Register
Set w/o
DLL reset
OCD Drive(1)
or
OCD default
OCD
calibration
mode exit
Figure 8 Initialization Sequence after Power Up
2.2.2 Programming the Mode Register and Extended Mode Registers
For application flexibility, burst length, burst type, CAS
latency, DLL reset function, write recovery time (t_WR)
are user defined variables and must be programmed
with a Mode Register Set (MRS) command.
Additionally, DLL disable function, additive CAS
latency, driver impedance, On Die Termination (ODT),
single-ended strobe and Off Chip Driver impedance
adjustment (OCD) are also user defined variables and
must be programmed with an Extended Mode Register
Set (EMRS) command.
Contents of the Mode Register (MRS) or Extended
Mode Registers (EMRS(#)) can be altered by re-
executing the MRS and EMRS Commands. If the user
chooses to modify only a subset of the MRS or EMRS
variables, all variables must be redefined when the
MRS or EMRS commands are issued.
Also any programming of EMRS(2) or EMRS(3) must
be followed by programming of MRS and EMRS(1).
After initial power up, all MRS and EMRS Commands
must be issued before read or write cycles may begin.
All banks must be in a precharged state and CKE must
be high at least one cycle before the Mode Register Set
Command can be issued. Either MRS or EMRS
Commands are activated by the low signals of CS,
RAS, CAS and WE at the positive edge of the clock.
When both bank addresses BA[1:0] are low, the DDR2
SDRAM enables the MRS command. When the bank
addresses BA0 is high and BA1 is low, the DDR2
SDRAM enables the EMRS(1) command.
The address input data during this cycle defines the
parameters to be set as shown in the MRS and EMRS
table. A new command may be issued after the mode
register set command cycle time (t_MRD).
MRS, EMRS and DLL Reset do not affect array
contents, which means reinitialization including those
can be executed any time after power-up without
affecting array contents.
2.2.2.1 DDR2 SDRAM Mode Register Set (MRS)
The mode register stores the data for controlling the
various operating modes of DDR2 SDRAM. It programs
CAS latency, burst length, burst sequence, test mode,
DLL reset, Write Recovery (WR) and various vendor
specific options to make DDR2 SDRAM useful for
various applications.
The default value of the mode register is not defined,
therefore the mode register must be written after
power-up for proper operation. The mode register is
written by asserting low on CS, RAS, CAS, WE,
BA[1:0], while controlling the state of address pins
A[13:0]. The DDR2 SDRAM should be in all bank
precharged (idle) mode with CKE already high prior to
writing into the mode register. The mode register set
command cycle time (t_MRD) is required to complete the
write operation to the mode register. The mode register
contents can be changed using the same command
and clock cycle requirements during normal operation
as long as all banks are in the precharged state. The
mode register is divided into various fields depending
on functionality.
Burst length is defined by A[2:0] with options of 4 and 8
bit burst length. Burst address sequence type is defined
by A3 and CAS latency is defined by A[6:4]. A7 is used
for test mode and must be set to low for normal MRS
operation. A8 is used for DLL reset. A[11:9] are used for
write recovery time (t_WR) definition for Auto-Precharge
mode. With address bit A12 two Power-Down modes
can be selected, a “standard mode” and a “low-power”
Power-Down mode, where the DLL is disabled.
Address bit A13 and all “higher” address bits have to
be set to “low” for compatibility with other DDR2
memory products with higher memory densities.
Data Sheet
23
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P