HYB18T512400AC5 Datasheet, PDF (26/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Field Bits
OCD [9:7]
Program
DQS
10
RDQS 11
Qoff
12
Type¹⁾ Description (cont’d)
w
Off-Chip Driver Calibration Program
Every calibration mode command should be followed by “OCD calibration mode exit”
before any other command will be issued; see Chapter 2.3.
000 OCD calibration mode exit, maintain setting
001 Drive 1
010 Drive 0
100 Adjust mode
Note: When Adjust Mode is issued, AL from previously set value must be applied.
111 OCD calibration default
Note: After setting to default, OCD mode needs to be exited by setting A[9:7] to 000.
w
Complement Query Strobe (DQS, RDQS Output)
If enabled the complement query strobe (DQS output) is driven high one clock cycle
before valid query data (DQ) is driven onto the data bus; see Chapter 2.6.3.
0 Enable
1 Disable
w
Read Data Strobe Output (RDQS, RDQS)
0 Disable
1 Enable
w
Output Disable
Disabling the DRAM outputs (DQ, DQS, DQS, RDQS, RDQS) allows users to
measure I_DD during Read operations without including the output buffer current.
0 Output buffers enabled
1 Output buffers disabled
1) w = write only register bits
A0 is used for DLL enable or disable. A1 is used for
enabling half-strength data-output driver. A2 and A6
enables ODT (On-Die termination) and sets the Rtt
value. A[5:3] are used for additive latency settings and
A[9:7] enables the OCD impedance adjustment mode.
A10 enables or disables the differential DQS and
RDQS signals, A11 disables or enables RDQS.
Address bit A12 have to be set to “low” for normal
operation. With A12 set to “high” the SDRAM outputs
are disabled and in Hi-Z. “High” on BA0 and “low” for
BA1 have to be set to access the EMRS(1). A13 and all
“higher” address bits have to be set to “low” for
compatibility with other DDR2 memory products with
higher memory densities. Refer to Mode Register
Definition (BA[1:0] = 00_B).
Single-ended and Differential Data Strobe Signals
Table 8 lists all possible combinations for DQS, DQS,
RDQS, RQDS which can be programmed by A[11:10]
address bits in EMRS. RDQS and RDQS are available
in ×8 components only.
If RDQS is enabled in ×8 components, the DM function
is disabled. RDQS is active for reads and don’t care for
writes.
Table 8 Single-ended and Differential Data Strobe Signals
EMRS(1)
Strobe Function Matrix
A11
A10
RDQS/DM RDQS
(RDQS Enable) (DQS Enable)
DQS
0 (Disable)
0 (Enable) DM
Hi-Z
DQS
0 (Disable)
1 (Disable) DM
Hi-Z
DQS
1 (Enable)
0 (Enable) RDQS
RDQS DQS
1 (Enable)
1 (Disable) RDQS
Hi-Z
DQS
DLL Enable/Disable
DQS
DQS
Hi-Z
DQS
Hi-Z
Signaling
differential DQS signals
single-ended DQS signals
differential DQS signals
single-ended DQS signals
Data Sheet
26
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P