HYB18T512400AC5 Datasheet, PDF (44/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK, CK
W rite to Read = (CL - 1)+ BL/2 +tW TR(2) = 6
CMD
NOP
NOP
NOP
NOP
Post CAS
NOP
NOP
NOP
NOP
READ A
DQS,
DQS
DQ
WL = RL - 1 = 4
DIN A0 DIN A1 DIN A2 DIN A3
AL=2
tW TR
CL=3
RL=5
BWBR
Figure 32 Write followed by Burst Read Example: RL = 5 (AL = 2, CL = 3), WL = 4, t_WTR = 2, BL = 4
The minimum number of clocks from the write command to the read command is (CL - 1) +BL/2 + t_WTR, where t_WTR
is the write-to-read turn-around time t_WTR expressed in clock cycles. The t_WTR is not a write recovery time (t_WR) but
the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD Post CAS
W R ITE A
NOP
Post CAS
W RITE B
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
DQ
WL = RL - 1 = 4
DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3
SBR
Figure 33 Seamless Write Operation Example 1: RL = 5, WL = 4, BL = 4
The seamless write operation is supported by enabling a write command every BL/2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
Data Sheet
44
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P