HYB18T512400AC5 Datasheet, PDF (65/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Truth Tables
3
Truth Tables
Table 16 Command Truth Table
Function
(Extended) Mode
Register Set
CKE
CS RAS CAS WE BA0 A[13:11] A10 A[9:0]
Previous Current
BA1
Cycle Cycle
H
H
L L L L BA OP Code
Notes
1)2)3)4)
5)
Auto-Refresh
H
Self-Refresh Entry
H
Self-Refresh Exit
L
Single Bank Precharge H
H
LL L H X X
L
LL L H X X
H
HX X X X X
H
L L H L BA X
XX
XX
6)
XX
6)
LX
5)
Precharge all Banks H
Bank Activate
H
Write
H
Write with Auto-
H
Precharge
H
LL H L X X
HX
H
L L H H BA Row Address
5)
H
L H L L BA Column L Column ⁵⁾⁷⁾
H
L H L L BA Column H Column ⁵⁾⁷⁾
Read
H
Read with Auto-
H
Precharge
H
L H L H BA Column L Column ⁵⁾⁷⁾
H
L H L H BA Column H Column ⁵⁾⁷⁾
No Operation
H
X
LH H H X X
XX
Device Deselect
H
Power Down Entry
H
X
HX X X X X
L
HX X X X X
XX
XX
8)
Power Down Exit
L
LH H H
H
HX X X X X
XX
4)8)
LH H H
1) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
2) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
3) “X” means “H or L (but a defined logic level)”.
4) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
5) Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BAx selects an (Extended) Mode
Register.
6) V_REF must be maintained during Self refresh Operation
7) Burst reads or writes at BL = 4 cannot be terminated.
8) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the
refresh requirements outlined in Chapter 2.9.
Data Sheet
65
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P