HYB18T512400AC5 Datasheet, PDF (25/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.2.3 DDR2 SDRAM Extended Mode Register Set (EMRS(1))
The Extended Mode Register EMRS(1) stores the data
for enabling or disabling the DLL, output driver
strength, additive latency, OCD program, ODT, DQS
and output buffers disable, RQDS and RDQS enable.
The default value of the extended mode register
EMRS(1) is not defined, therefore the extended mode
register must be written after power-up for proper
operation. The extended mode register is written by
asserting low on CS, RAS, CAS, WE, BA1 and high on
BAO, while controlling the state of the address pins.
The DDR2 SDRAM should be in all bank precharge
with CKE already high prior to writing into the extended
mode register. The mode register set command cycle
time (t_MRD) must be satisfied to complete the write
operation to the EMRS(1). Mode register contents can
be changed using the same command and clock cycle
requirements during normal operation as long as all
banks are in precharge state.
EMR(1)
Extended Mode Register Definition
(BA[1:0] = 01_B)
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1
0¹⁾
Q RDQS DQS
OCD Program
Rtt
AL
Rtt DIC DLL
reg. addr
OFF w
w
w
w
w
w
w
w
1) A13 is only available for ×4 and ×8 configuration.
Field
DLL
DIC
R_TT
AL
Bits Type¹⁾ Description
0
w
DLL Enable
The DLL must be enabled for normal operation. See .
0 Enable
1 Disable
1
w
Off-chip Driver Impedance Control
0 Normal (Driver Size = 100%)
1 Weak (Driver Size = 60%)
2,6 w
Nominal Termination Resistance of ODT
Note: All other bit combinations are RESERVED.
[5:3] w
00 ∞ (ODT disabled)
10 75 Ohm
01 150 Ohm
Additive Latency
The additive latency must be programmed into the device to delay all read and write
commands; see Chapter 2.5.
Note: All other bit combinations are RESERVED.
000 0
001 1
010 2
011 3
100 4
Data Sheet
25
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P