HYB18T512400AC5 Datasheet, PDF (61/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
CK, CK
Tn
Tn+1
Tn+2
CM D _{W RITE}
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
V a lid
NOP
Com m and
CKE
DQS,
DQS
DQ
tIS
WL + BL/2 + tWTR
WL = RL - 1 = 2
DIN A0 DIN A1 DIN A2 DIN A3
tWTR
tIS
tXARD or
tXARDS *)
Active
Power-Down
Entry
Active
Power-Down
Exit
Act.PD 2
Figure 56 Active Power-Down Mode Entry and Exit Example after a Write Command:
WL = 2, t_WTR = 2, BL = 4
Note: Active Power-Down mode exit timing t_XARD (“fast exit”) or t_XARDS (“slow exit”) depends on the programmed
state in the MRS, address bit A12.
T0
T1
T2
T3
T4
T5
T6
T7
CK, CK
Tn
Tn+1
Tn+2
CM D ^{W RITE}
NOP
w /A P
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
V a lid
NOP
Command
CKE
DQS,
DQS
WL = RL - 1 = 2
WL + BL/2 + WR
tIS
WR
DQ
DIN A0 DIN A1 DIN A2 DIN A3
tIS
tXARD or
tXARDS *)
Active
Power-Down
Entry
Active
Power-Down
Exit
Act.PD 3
Figure 57 Active Power-Down Mode Entry and Exit Example after a Write Command with AP:
WL = 2, WR = 3, BL = 4
Note: Active Power-Down mode exit timing t_XARD (“fast exit”) or t_XARDS (“slow exit”) depends on the programmed
state in the MRS, address bit A12. WR is the programmed value in the MRS mode register.
Data Sheet
61
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P