HYB18T512400AC5 Datasheet, PDF (30/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
For proper operation of adjust mode, WL = RL - 1 =
AL + CL - 1 clocks and t_DS / t_DH should be met as
Figure 10. Input data pattern for adjustment, DT[0:3] is
fixed and not affected by MRS addressing mode (i.e.
sequential or interleave).
Burst length of 4 have to be programmed in the MRS for
OCD impedance adjustment.
CK, CK
CMD
EMRS(1)
NOP
WL
DQS_in
DQ_in
DM
NOP
NOP
DQS
tDS tDH
DT0 DT1 DT2 DT3
NOP
OCD adjust mode
NOP
NOP
tWR
EMRS(1)
NOP
OCD calibration
OCD1
mode exit
Figure 10 Timing Diagram Adjust Mode
Drive Mode
Drive mode, both Drive(1) and Drive(0), is used for
controllers to measure DDR2 SDRAM Driver
impedance before OCD impedance adjustment. In this
mode, all outputs are driven out t_OIT after “enter drive
mode” command and all output drivers are turned-off
t_OIT after “OCD calibration mode exit” command. See
Figure 11.
CK, CK
CMD
EMRS(1)
tOIT
NOP
NOP
NOP
NOP
EMRS(1)
tOIT
NOP
NOP
DQS_in
DQ_in
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0
DQS high for Drive(1)
DQS high for Drive(0)
Enter Drive Mode
Figure 11 Timing Diagram Drive Mode
OCD calibration
mode exit
NOP
OCD2
Data Sheet
30
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P