HYB18T512400AC5 Datasheet, PDF (41/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T
0
CK, CK
CM
D
READ A
T
1
NOP
T
2
NOP
DQS,
DQS
DQ'
s
CL = 3
RL = 3
T
T
T
T
T
3
4
5
6
7
NOP
NOP
<= tDQSCK
NOP
NOP
NOP
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5
Dout A6 Dout A7
Figure 25 Read Operation Example 2: RL = 3 (AL = 0, CL = 3, BL = 8)
T
8
NOP
BRead303
T
T
0
1
CK, CK
T
T
T
T
T
T
T
3
4
5
6
7
8
9
CMD
Posted CAS
READ A
DQS,
DQS
DQ
NOP
NOP
BL/2 + 2
Posted CAS
WRITE A
RL = 5
NOP
NOP
NOP
WL = RL - 1 = 4
Dout A0 Dout A1
Dout A2 Dout A3
NOP
NOP
Din A0
Din A1
Din A2
Din A3
BRBW514
Figure 26 Read followed by Write Example: RL = 5, WL = (RL-1) = 4, BL = 4
The minimum time from the read command to the write command is defined by a read-to-write turn-around time,
which is BL/2 + 2 clocks.
Data Sheet
41
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P