HYB18T512400AC5 Datasheet, PDF (87/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
CK,DQS
CK,DQS
V _DDQ
V _{IH (ac)} min
V _{IH (dc)} min
V _REF
VREF to ac
region
V _{IL (dc)} max
V _{IL (ac)} max
V _SS
Nominal
line
t _IS ,t _DS
tIH _{,t DH}
t _IS ,t _DS tIH ,t _DH
Nominal
line
Tangent
line
Tangent
line
VREF to ac
region
Delta TR
Delta TF
Setup Slew Rate
Falling Signal
=
Setup Slew Rate
Rising Signal ⁼
tangent line [VREF(dc) - VIL(ac)max]
Delta TF
tangent line [VIH(ac)min - VREF(dc)]
Delta TR
Figure 71 Slew Rate Definition Tangent Diagram for t_IS(t_DS)
Note: DQS, DQS signals must be monotonic between V_IL(dc)max and V_IH(dc)min.
Data Sheet
87
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P