HYB18T512400AC5 Datasheet, PDF (62/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
T1
T2
CK, CK
CMD
CKE
Precharge
NOP
tIS
tRP
NOP
Precharge
Power-Down
Entry
T3
NOP
Tn
Tn+1
Tn+2
NOP
NOP
NOP
tIS
tXP
Valid
Command
NOP
Precharge
Power-Down
Exit
Figure 58 Precharge Power Down Mode Entry and Exit
Note: "Precharge" may be an external command or an internal precharge following Write with AP.
T0
T1
T2
T3
T4
Tn
CK, CK
CMD
CKE
Auto
Refresh
tRFC
tXP
tis
CKE can go low one clock after an Auto-Refresh command
When tRFC expires the DRAM is in Precharge Power-Down Mode
Figure 59 Auto-Refresh command to Power-Down entry
T0
T1
T2
T3
T4
T5
T6
T7
CK, CK
CMD
MRS or
EMRS
t_MRD
CKE
Enters Precharge Power-Down Mode
Figure 60 MRS, EMRS command to Power-Down entry
Valid
Command
ARPD
MRS_PD
Data Sheet
62
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P