HYB18T512400AC5 Datasheet, PDF (51/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.7.2 Write followed by Precharge
Minimum Write to Precharge command spacing to the
same bank = WL + BL/2 + t_WR. For write cycles, a delay
must be satisfied from the completion of the last burst
write cycle until the Precharge command can be
issued. This delay is known as a write recovery time
(t_WR) referenced from the completion of the burst write
to the Precharge command. No Precharge command
should be issued prior to the t_WR delay, as DDR2
SDRAM does not support any burst interrupt by a
Precharge command. t_WR is an analog timing
parameter (see Chapter 7) and is not the programmed
value for t_WR in the MRS.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD Post CAS
W R ITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
WL = 3
Com pletion of
the Burst W rite
tW R
DQ
DIN A0 DIN A1 DIN A2 DIN A3
Figure 44 Write followed by Precharge Example 1: WL = (RL - 1) = 3, BL = 4, t_WR = 3
P re c h a rg e
A
BW-P3
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
CMD Post CAS
W RITE A
DQS,
DQS
DQ
NOP
NOP
WL = 4
NOP
NOP
NOP
NOP
NOP
Com pletion of
the Burst W rite
tW R
DIN A0 DIN A1 DIN A2 DIN A3
Figure 45 Write followed by Precharge Example 2: WL = (RL - 1) = 4, BL = 4, t_WR = 3
P re ch a rg e
A
BW-P4
Data Sheet
51
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P