HYB18T512400AC5 Datasheet, PDF (40/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
CLK, CLK
CLK
CLK
DQS,
DQS
DQ
t CH
t _CL
t _CK
t _DQSCK
t AC
DQS
DQS
t _RPRE
t LZ
t RPST
t _HZ
t DQSQmax
Dout
t QH
Dout
Dout
t _DQSQmax
Dout
t QH
Figure 23 Basic Read Timing Diagram
DO-Read
T
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
8
CK, CK
CMD
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
<= tDQSCK
NOP
NOP
DQS,
DQS
DQ
AL = 2
RL = 5
CL = 3
Dout A0 Dout A1
Dout A2 Dout A3
BRead523
Figure 24 Burst Operation Example 1: RL = 5 (AL = 2, CL = 3, BL = 4)
The seamless read operation is supported by enabling a read command at every BL / 2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
Data Sheet
40
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P