HYB18T512400AC5 Datasheet, PDF (37/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
beginning with the column address supplied to the
device during the Read or Write Command (CA[9:0] &
CA11).
A new burst access must not interrupt the previous 4 bit
burst operation in case of BL = 4 setting. Therefore the
minimum CAS to CAS delay (t_CCD) is a minimum of 2
clocks for read or write cycles.
For 8 bit burst operation (BL = 8) the minimum CAS to
CAS delay (t_CCD) is 4 clocks for read or write cycles.
Burst interruption is allowed with 8 bit burst operation.
For details see Chapter 2.6.6.
T
T
T
T
T
T
T
T
0
1
2
3
4
5
6
7
CK, CK
CMD READ A
DQS,
DQS
NOP
tCCD
READ B
NOP
tCCD
READ C
NOP
NOP
NOP
T12
NOP
NOP
DQ
Dout A0 Dout A1
Dout A2 Dout A3 Dout B0 Dout B1
Dout B2 Dout B3 Dout C0 Dout C1
Dout C2 Dout C3
RB
Figure 18 Read Burst Timing Example: (CL = 3, AL = 0, RL = 3, BL = 4)
2.6.1 Posted CAS
Posted CAS operation is supported to make command
and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. In this operation, the DDR2 SDRAM
allows a Read or Write command to be issued
immediately after the RAS bank activate command (or
any time during the RAS to CAS delay time, t_RCD
period). The command is held for the time of the
Additive Latency (AL) before it is issued inside the
device. The Read Latency (RL) is the sum of AL and
the CAS latency (CL). Therefore if a user chooses to
issue a Read/Write command before the t_{RCD, min}, then
AL greater than 0 must be written into the EMRS(1).
The Write Latency (WL) is always defined as RL - 1
(Read Latency -1) where Read Latency is defined as
the sum of Additive Latency plus CAS latency
(RL=AL+CL). If a user chooses to issue a Read
command after the t_{RCD, min} period, the Read Latency is
also defined as RL = AL + CL.
01
2 34
5
CK, CK
CMD
DQS,
DQS
DQ
Activate
Bank A
Read
Bank A
AL = 2
Write
Bank A
CL = 3
tRCD
RL = AL + CL = 5
6
7
8
WL = RL -1 = 4
Dout0
Dout1
Dout2
Dout3
9 10 11
Din0
Din1
Din2
Din3
PostCAS1
Figure 19 Activate to Read Timing Example : Read followed by a write to the same bank, Activate to
Read delay < t_RCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
Data Sheet
37
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P