HYB18T512400AC5 Datasheet, PDF (21/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

2
Functional Description
2.1
Simplified State Diagram
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Initialization
Sequence
CKEL
Precharge
PD
Auto
Refreshing
REFSX
t_RFC
REFS
Self
Refresh
CKEL
PD_entry
MRS
Setting
Idle
MRS or
CKEH
t_MRD ^EMRS
Activating
WL + BL/2 + WR
Writing_AP
t_RCD
t_RP
Precharging
RL + BL/2 + t_RTP
Reading_AP
Write
Writing
Read
Reading
CKEL
Active PD
PD_entry
CKEH
Write
Read
Bank
Active
Automatic Sequence
Command Sequence
Figure 7 Simplified State Diagram
Note: This Simplified State Diagram is intended to
provide a floorplan of the possible state
transitions and thecommands to control them. In
particular situations involving more than one
MPFT0010
bank, enabling / disabling on-die termination,
Power-Down entry / exit - among other things -
are not captured in full detail.
Data Sheet
21
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P