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| HYB18T512400AC5 Datasheet, PDF (70/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM | |||
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HYB18T512[400/800/160]A[C/F]â[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions
Table 26 Differential DC and AC Input and Output Logic Levels
Symbol
VIN(dc)
VID(dc)
VID(ac)
VIX(ac)
VOX(ac)
Parameter
DC input signal voltage
DC differential input voltage
AC differential input voltage
AC differential cross point input
voltage
AC differential cross point output
voltage
Min.
â0.3
0.25
0.5
0.5 Ã VDDQ â 0.175
Max.
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.5 Ã VDDQ + 0.175
Units
V
V
Notes
1)
2)
3)
4)
0.5 Ã VDDQ â 0.125 0.5 Ã VDDQ + 0.125 V
5)
1) VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
2) VID(dc) specifies the input differential voltage VTRâ VCP required for switching. The minimum value is equal to VIH(dc) â VIL(dc).
3) VID(ac) specifies the input differential voltage VTR â VCP required for switching. The minimum value is equal to VIH(ac) â VIL(ac).
4) The value of VIX(ac) is expected to equal 0.5 Ã VDDQ of the transmitting device and VIX(ac) is expected to track variations in
VDDQ. VIX(ac) indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 Ã VDDQ of the transmitting device and VOX(ac) is expected to track variations in
VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross.
VTR
VID
Crossing Point
VDDQ
VCP
VIX or VOX
SSTL18_3
Figure 64 Differential DC and AC Input and Output Logic Levels Diagram
VSSQ
Data Sheet
70
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
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