HYB18T512400AC5 Datasheet, PDF (34/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Mode entry:
As long as the timing parameter t_{ANPD, min} is satisfied
when ODT is turned on or off before entering these
power-down modes, synchronous timing parameters
can be applied. If t_{ANPD, min} is not satisfied,
asynchronous timing parameters apply.
T-
5
CK, CK
CKE
ODT turn-off, tANPD >= 3 tCK :
ODT
ODT turn-off, tANPD <3 tCK :
ODT
ODT turn-on, tANPD >= 3 tCK :
ODT
ODT turn-on, tANPD < 3 tCK :
ODT
T-
T-
T-
T-
T
T
T
4
3
2
1
0
1
2
tANPD (3 tCK)
t
IS
t
IS
RTT
tAOFD
RTT
tAOFPDmax
t
IS
tAOND
RTT
t
IS
tAONPDmax
RTT
ODT0
3
Synchronou
timings
apply
Asynchronou
timings
apply
Synchronou
timings
apply
Asynchronou
timings
apply
Figure 15 ODT Mode entry Timing Diagram
Data Sheet
34
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P