HYB18T512400AC5 Datasheet, PDF (54/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
P osted CAS
R EAD w/AP
NOP
A10 ="high"
DQS,
DQS
DQ
AL = 1
NOP
NOP
AL + BL/2
NOP
NOP
NOP
tRP
Auto-Precharge Begins
NOP
Bank
A c tiv a te
CL = 3
RL = 4
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7
>= tRTP
first 4-bit prefetch
second 4-bit prefetch
BR-AP413(8)2
Figure 48 Read with Auto-Precharge Example 3, followed by an Activation to the Same Bank:
RL = 4 (AL = 1, CL = 3), BL = 8, t_RTP ≤ 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
P osted CAS
R EAD w/AP
NOP
NOP
NOP
NOP
NOP
NOP
Bank
A c tiv a te
NOP
A10 ="high"
AL + tRTP + tRP
DQS,
DQS
AL = 1
Auto-Precharge Begins
CL = 3
RL = 4
DQ
Dout A0 Dout A1 Dout A2 Dout A3
tRTP
tRP
first 4-bit prefetch
BR-AP4133
Figure 49 Read with Auto-Precharge Example 4, followed by an Activation to the Same Bank:
RL = 4 (AL = 1, CL = 3), BL = 4, t_RTP > 2 clocks
Data Sheet
54
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P