HYB18T512400AC5 Datasheet, PDF (77/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
I_DD Specifications and Conditions
6
I_DD Specifications and Conditions
Table 36 I_DD Measurement Conditions
Parameter
Symbol Notes
1)2)3)4)5)6)
Operating Current 0
I_DD0
One bank Active - Precharge; t_CK = t_CKmin., t_RC = t_RCmin., t_RAS = t_RASmin., CKE is HIGH, CS is
high between valid commands. Address and control inputs are SWITCHING, Databus inputs
are SWITCHING.
Operating Current 1
I_DD1
One bank Active - Read - Precharge; I_OUT = 0 mA, BL = 4, t_CK = t_CKmin., t_RC = t_RCmin., t_RAS =
t_RASmin., t_RCD = t_RCDmin.,AL = 0, CL = CL_min.; CKE is HIGH, CS is high between valid commands.
Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Power-Down Current
I_DD2P
All banks idle; CKE is LOW; t_CK = t_CKmin;Other control and address inputs are STABLE, Data
bus inputs are FLOATING.
Precharge Standby Current
I_DD2N
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CKmin.; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current
I_DD2Q
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CKmin.; Other control and address inputs are
STABLE, Data bus inputs are FLOATING.
Active Power-Down Current
I_DD3P(0)
All banks open; t_CK = t_CKmin., CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
Active Power-Down Current
I_DD3P(1)
All banks open; t_CK = t_CKmin., CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current
I_DD3N
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_min.; t_CK = t_CKmin.;
t_RAS = t_RASmax., t_RP = t_RPmin.; CKE is HIGH, CS is high between valid commands. Address inputs
are SWITCHING; Data Bus inputs are SWITCHING; I_OUT = 0 mA.
Operating Current
I_DD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_min.; t_CK = t_CKmin.;
t_RAS = t_RASmax., t_RP = t_RPmin.; CKE is HIGH, CS is high between valid commands. Address inputs
are SWITCHING; Data Bus inputs are SWITCHING; I_OUT = 0 mA.
Operating Current
I_DD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_min.; t_CK = t_CKmin.;
t_RAS = t_RASmax., t_RP = t_RPmin.; CKE is HIGH, CS is high between valid commands. Address inputs
are SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t_CK = t_CKmin., Refresh command every t_RFC = t_RFCmin. interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus
inputs are SWITCHING.
I_DD5B
Distributed Refresh Current
t_CK = t_CKmin., Refresh command every t_RFC = t_REFI interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus
inputs are SWITCHING.
I_DD5D
Data Sheet
77
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P