HYB18T512400AC5 Datasheet, PDF(84/96 Page) Infineon Technologies AG

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HYB18T512400AC5 Datasheet, PDF (84/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

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HYB18T512[400/800/160]A[C/F]â[3.7/5]

512-Mbit Double-Data-Rate-Two SDRAM

Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating

8.3

Input and Data Setup and Hold Time

8.3.1

Timing Definition for Input Setup (tIS) and Hold Time (tIH)

Address and control input setup time (tIS) is referenced

from the input signal crossing at the VIH(ac) level for a

rising signal and VIL(ac) for a falling signal applied to the

device under test. Address and control input hold time

(tIH) is referenced from the input signal crossing at the

VIL(dc) level for a rising signal and VIH(dc) for a falling

signal applied to the device under test.

t IS t IH

tIS tIH

Figure 68 Input, setup and Hold Time Diagram

VDDQ

VIH(ac) min

VIH(dc) min

VREF

VIL(dc) max

VIL(ac) max

VSS

8.3.2

Timing Definition for Data Setup (tDS) and Hold Time (tDH)

1. Data input setup time with differential data strobe 2. Data input hold time with differential data strobe

enabled MR[bit10]=0, is referenced from the input

signal crossing at the VIH(ac) level to the differential

data strobe crosspoint for a rising signal, and from

the input signal crossing at the VIL(ac) level to the

differential data strobe crosspoint for a falling signal

signal crossing at the VIL(dc) level to the differential

data strobe crosspoint for a rising signal and VIH(dc)

to the differential data strobe crosspoint for a falling

signal applied to the device under test. Input

applied to the device under test. Input waveform

waveform timing with single-ended data strobe

timing with single-ended data strobe enabled

enabled MR[bit10]=1, is referenced from the input

MR[bit10]=1, is referenced from the input signal

crossing at the VIH(ac) level to the data strobe

crossing VREF for a rising signal, and from the input

signal crossing at the VIL(ac) level to the single-

ended data strobe crossing VREF for a falling signal

applied to the device under test.

signal crossing at the VIL(dc) level to the single-

ended data strobe crossing VREF for a rising signal

and VIH(dc) to the single-ended data strobe crossing

VREF for a falling signal applied to the device under

test.

Data Sheet

Rev. 1.13, 2004-05

09112003-SDM9-IQ3P

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