HYB18T512400AC5 Datasheet, PDF (35/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Mode exit:
As long as the timing parameter t_{AXPD, min} is satisfied
when ODT is turned on or off after exiting these power-
down modes, synchronous timing parameters can be
applied. If t_{AXPD, min} is not satisfied, asynchronous timing
parameters apply.
T
T
0
1
T
T
T
T
T
5
6
7
8
9
T10
CK, CK
t _IS
CKE
tAXPD
ODT turn-off, tAXPD >= tAXPDmin:
Synchronous
timings apply
ODT turn-off, tAXPD < tAXPDmin:
Asynchronous
timings apply
ODT turn-on, tAXPD >= tAXPDmin:
Synchronou s
timings apply
ODT
ODT
ODT
ODT turn-on, tAXPD < tAXPDmin:
Asynchronous
ODT
timings apply
Figure 16 ODT Mode exit Timing Diagram
t _IS
t _IS
Rtt
Rtt
tAOFD
tAOFPDmax
t _IS
Rtt
t _IS
tAOND
tAONPDmax
Rtt
ODT04
2.5
Bank Activate Command
The Bank Activate command is issued by holding CAS
and WE high with CS and RAS low at the rising edge of
the clock. The bank addresses BA[1:0] are used to
select the desired bank. The row addresses A0 through
A13 are used to determine which row to activate in the
selected bank for ×4 and ×8 organised components.
For ×16 components row addresses A0 through A12
have to be applied. The Bank Activate command must
be applied before any Read or Write operation can be
executed. Immediately after the bank active command,
the DDR2 SDRAM can accept a read or write command
(with or without Auto-Precharge) on the following clock
cycle. If a R/W command is issued to a bank that has
not satisfied the t_{RCD, min} specification, then additive
latency must be programmed into the device to delay
the R/W command which is internally issued to the
device. The additive latency value must be chosen to
assure t_{RCD, min} is satisfied. Additive latencies of 0, 1, 2,
3 and 4 are supported. Once a bank has been activated
it must be precharged before another Bank Activate
command can be applied to the same bank. The bank
active and precharge times are defined as t_RAS and t_RP,
Data Sheet
35
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P