HYB18T512400AC5 Datasheet, PDF (12/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Overview
Table 3 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name Pin Buffer Function
Type Type
E1, J9, M9, R1 V_DD
E7, F2, F8, H2, V_SSQ
H8
PWR –
PWR –
Power Supply
Power Supply
J7
V_SSDL
PWR –
J3,N1,P9
V_SS
PWR –
Not Connected ×4/×8 organizations
Power Supply
Power Supply
L3,L7, G1
NC
NC
–
Not Connected
Not Connected ×4 organization
A2, B1, B9, NC
D1, D9
NC
–
Not Connected
Not Connected ×16 organization
A2, E2, L1, R3, NC
R7, R8
NC
–
Not Connected
Other Pins ×4/×8 organizations
F9
ODT
–
–
On-Die Termination Control
Other Pins ×16 organization
K9
ODT
–
–
On-Die Termination Control
Table 4
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
Table 5
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Data Sheet
12
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P