HYB18T512400AC5 Datasheet, PDF (31/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
2.4
On-Die Termination (ODT)
On-Die Termination (ODT) is a new feature on DDR2
components that allows a DRAM to turn on/off
termination resistance for each DQ, DQS, DQS, DM for
×4 and DQ, DQS, DQS, DM, RDQS (DM/RDQS share
the same pin), RDQS for ×8 configuration via the ODT
control pin. DQS is terminated only when enabled in the
EMRS(1) by address bit A10 = 0. For ×8 configuration
RDQS is only terminated, when enabled in the
EMRS(1) by address bits A10 = 0 and A11 = 1.
For ×16 configuration ODT is applied to each DQ,
UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via
the ODT control pin. UDQS and LDQS are terminated
only when enabled in the EMRS(1) by address bit
A10 = 0.
The ODT feature is designed to improve signal integ-
rity of the memory channel by allowing the DRAM con-
troller to independently turn on/off termination
resistance for any or all DRAM devices.
The ODT function can be used for all active and
standby modes. ODT is turned off and not supported in
Self-Refresh mode.
VDDQ
VDDQ
sw1
sw2
DRAM
Input
Buffer
Rval1
Rval2
Rval1
Rval2
Input
Pin
sw1
sw2
VSSQ
VSSQ
Figure 12 Functional Representation of ODT
Switch sw1 or sw2 is enabled by the ODT pin. Selection
between sw1 or sw2 is determined by “Rtt (nominal)” in
EMRS(1) address bits A6 & A2.
Target Rtt = 0.5 × Rval1 or 0.5 × Rval2.
The ODT pin will be ignored if the Extended Mode
Register (EMRS(1)) is programmed to disable ODT.
Data Sheet
31
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P