HYB18T512400AC5 Datasheet, PDF (81/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Electrical Characteristics & AC Timing - Absolute Specification
Table 40 Timing Parameter by Speed Grade - DDR2-400 & DDR2-533^1)2)3)4)5)6)
Symbol Parameter
–5
–3.7
Unit Notes
DDR2–400 3–3–3 DDR2–533 4–4–4
t_RFC
Auto-Refresh to Active/Auto-Refresh
command period
t_RCD
Active to Read or Write delay
(with and without Auto-Precharge)
Min.
105
15
Max.
—
—
Min.
105
15
Max.
—
—
ns ¹⁷⁾
ns ¹⁸⁾
t_RP
Precharge command period
15
—
t_RRD
Active bank A to Active bank B command 7.5
—
period
10
—
15
—
7.5
—
10
—
ns
ns ¹⁹⁾
ns ²⁰⁾
t_CCD
t_WR
t_DAL
t_WTR
t_RTP
t_XARD
t_XARDS
CAS A to CAS B command period
Write recovery time
Auto-Precharge write recovery +
precharge time
Internal Write to Read command delay
Internal Read to Precharge command
delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
2
15
—
WR + t_RP —
10
—
7.5
—
2
—
6 - AL —
2
15
—
WR + t_RP —
7.5
—
7.5
—
2
—
6 - AL —
t_CK
ns
t_CK ²¹⁾
ns ²²⁾
ns
t_CK ²³⁾
t_CK ²³⁾
t_XP
Exit precharge power-down to any valid 2
command (other than NOP or Deselect)
—
2
—
t_CK
t_XSRD
t_XSNR
t_CKE
t_REFI
Exit Self-Refresh to Read command
200
—
Exit Self-Refresh to non-Read command t_RFC+10 —
CKE minimum high and low pulse width 3
—
Average periodic refresh Interval
—
7.8
—
3.9
200
—
t_RFC+10
3
—
—
7.8
—
3.9
t_CK
ns
t_CK
µs
24)25)
26)
µs
t_OIT
t_DELAY
OCD drive mode output delay
0
12
Minimum time clocks remain ON after CKE t_IS+t_CK+t_IH —
asynchronously drops LOW
0
12
t_IS+t_CK+t_IH ––
ns
ns ²⁷⁾
1) V_DDQ = 1.8V ± 0.1V; V_DD = 1.8V ± 0.1V) See notes ^3)4)5)6)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. For other slew
rates see Chapter 8 of this datasheet.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS, t_IS, t_iH, t_DS, t_DH is V_REF.
For t_IS, t_iH, t_DS, t_DH input reference levels see Chapter 8.3 of this datasheet.
5) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is
recognized as LOW.
6) The output timing reference voltage level is V_TT. See Chapter 8 for the reference load for timing measurements.
7) Min (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for t_CL and t_CH).
8) For input frequency change during DRAM operation, see Chapter 2.12 of this datasheet.
Data Sheet
81
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P