HYB18T512400AC5 Datasheet, PDF (69/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
AC & DC Operating Conditions
5.2
DC & AC Logic Input Levels
DDR2 SDRAM pin timing are specified for either single
ended or differential mode depending on the setting of
the EMRS(1) “Enable DQS” mode bit; timing
advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin
timing are measured is mode dependent. In single
ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at
V_REF. In differential mode, these timing relationships
are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is
verified by design and characterization but not subject
to production test. In single ended mode, the DQS (and
RDQS) signals are internally disabled and don’t care.
Table 24
Symbol
V_IH(dc)
V_IL(dc)
V_IH(ac)
V_IL(ac)
Single-ended DC & AC Logic Input Levels
Parameter
Min.
DC input logic high
DC input low
V_REF + 0.125
–0.3
AC input logic high
AC input low
V_REF + 0.250
—
Max.
V_DDQ + 0.3
V_REF – 0.125
—
V_REF – 0.250
Units
V
V
V
V
Table 25 Single-ended AC Input Test Conditions
Symbol
V_REF
V_SWING(max)
SLEW
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
Value
0.5 x V_DDQ
1.0
1.0
Units
V
V
V / ns
Notes
1)2)
1)2)
3)4)
1.
1) This timing and slew rate definition is valid for all single-ended signals except t_IS, t_IH, t_DS, t_DH.
2) Input waveform timing is referenced to the input signal crossing through the V_REF level applied to the device under test.
3) The input signal minimum slew rate is to be maintained over the range from V_IL(dc)max to V_IH(ac)min for rising edges and the
range from V_IH(dc)min to V_IL(ac)max for falling edges as shown in Figure 63
4) AC timings are referenced with input waveforms switching from V_IL(ac) to V_IH(ac) on the positive transitions and V_IH(ac) to V_IL(ac
on the negative transitions.
Start of Falling Edge Input Timing
V_SWING(MAX)
delta TF
Falling Slew = ^{VIH(dc) min - VIL(ac) max}
delta TF
Start of Rising Edge Input Timing
delta TR
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
Rising Slew = ^{VIH(ac) min - VIL(dc) max}
delta TR
Figure 63 Single-ended AC Input Test Conditions Diagram
Data Sheet
69
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P