HYB18T512400AC5 Datasheet, PDF (86/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
CK,DQS
CK,DQS
V DDQ
V _{IH (ac)} min
V
IH (dc)
min
V _REF(dc)
V
IL (dc)
max
V
IL (ac)
max
t _IS ,t _DS
t _{IH ,t DH}
tIS ,t _DS tIH ,t _DH
Nominal
slew rate
Nominal
slew rate
V REF to ac
region
V _SS
Delta TF
Delta TR
Setup Slew Rate ₌ ^{Vref(dc) - VIL(ac)max}
Falling Signal
Delta TF
Setup Slew Rate ₌ ^{VIH(ac)min - VREF(dc)}
Rising Signal
Delta TR
Figure 70 Slew Rate Definition Nominal Diagram for t_IS(t_DS)
Note: DQS, DQS signals must be monotonic between V_IL(dc)max and V_IH(dc)min.
Data Sheet
86
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P