HYB18T512400AC5 Datasheet, PDF (45/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD _{W RITE A}
NOP
NOP
NOP
W RITE B
NOP
NOP
NOP
NOP
DQS,
DQS
DQ
WL = RL - 1 = 2
DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 _{DIN A5 DIN A5 DIN A7} DIN B0 DIN B1 DIN B2 DIN B3 ^{DIN B4} DIN B5 DIN B6 DIN B7
SBW_BL8
Figure 34 Seamless Write Operation Example 2: RL = 3, WL = 2, BL = 8, non interrupting
The seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every BL/2
number of clocks. This operation is allowed regardless of same or different banks as long as the banks are
activated.
2.6.5 Write Data Mask
One write data mask input (DM) for ×4 and ×8
components and two write data mask inputs (LDM,
UDM) for ×16 components are supported on DDR2
SDRAM’s, consistent with the implementation on DDR
SDRAM’s. It has identical timings on write operations
as the data bits, and though used in a uni-directional
manner, is internally loaded identically to data bits to
insure matched system timing. Data mask is not used
during read cycles. If DM is high during a write burst
coincident with the write data, the write data bit is not
written to the memory. For ×8 components the DM
function is disabled, when RDQS / RDQS are enabled
by EMRS(1).
DQS,
DQS
DQ
DM
t DQSH
DQS
DQS
t WPRE
t DQSL
D
t _DS
Mask
D
D
t DH
Mask
Mask
t _WPST
D
Mask
don't care
Figure 35 Write Data Mask Timing
Data Sheet
45
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P