HYB18T512400AC5 Datasheet, PDF (29/96 Pages) Infineon Technologies AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the
following EMRS(1) mode. In drive mode all outputs are
driven out by DDR2 SDRAM and drive of RDQS is
dependent on EMRS(1) bit enabling RDQS operation.
In Drive(1) mode, all DQ, DQS (and RDQS) signals are
driven high and all DQS (and RDQS) signals are driven
low. In Drive(0) mode, all DQ, DQS (and RDQS) signals
are driven low and all DQS (and RDQS) signals are
driven high. In adjust mode, BL = 4 of operation code
data must be used. In case of OCD calibration default,
output driver characteristics have a nominal impedance
value of 18 Ohms during nominal temperature and
voltage conditions. Output driver characteristics for
OCD calibration default are specified in Table 10. OCD
applies only to normal full strength output drive setting
defined by EMRS(1) and if half strength is set, OCD
default output driver characteristics are not applicable.
When OCD calibration adjust mode is used, OCD
default output driver characteristics are not applicable.
After OCD calibration is completed or driver strength is
set to default, subsequent EMRS(1) commands not
intended to adjust OCD characteristics must specify
A[9:7] as ’000’ in order to maintain the default or
calibrated value.
Table 9
A9
0
0
0
1
1
Output driver characteristics for OCD calibration
A8
A7
Operation
0
0
OCD calibration mode exit
0
1
Drive(1) DQ, DQS, (RDQS) high and DQS (RDQS) low
1
0
Drive(0) DQ, DQS, (RDQS) low and DQS (RDQS) high
0
0
Adjust mode
1
1
OCD calibration default
OCD impedance adjust
To adjust output driver impedance, controllers must
issue the ADJUST EMRS(1) command along with a 4
bit burst code to DDR2 SDRAM as in Table 10. For this
operation, Burst Length has to be set to BL = 4 via MRS
command before activating OCD and controllers must
drive the burst code to all DQs at the same time. DT0 in
Table 10 means all DQ bits at bit time 0, DT1 at bit time
1, and so forth. The driver output impedance is
adjusted for all DDR2 SDRAM DQs simultaneously and
after OCD calibration, all DQs of a given DDR2 SDRAM
will be adjusted to the same driver strength setting. The
maximum step count for adjustment is 16 and when the
limit is reached, further increment or decrement code
has no effect. The default setting may be any step
within the maximum step count range. When Adjust
mode command is issued, AL from previously set value
must be applied.
Table 10 Off- Chip-Driver Adjust Program
4 bit burst code inputs to all DQs
Operation
D_T0
D_T1
D_T2
D_T3
Pull-up driver strength
0
0
0
0
NOP (no operation)
0
0
0
1
Increase by 1 step
0
0
1
0
Decrease by 1 step
0
1
0
0
NOP
1
0
0
0
NOP
0
1
0
1
Increase by 1 step
0
1
1
0
Decrease by 1 step
1
0
0
1
Increase by 1 step
1
0
1
0
Decrease by 1 step
Other Combinations
Pull-down driver strength
NOP (no operation)
NOP
NOP
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Increase by 1 step
Decrease by 1 step
Decrease by 1 step
Reserved
Data Sheet
29
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P